This invention relates to a closed-loop synchronisation arrangement for a data transmission system, and in particular to an arrangement for a system which incorporates a high-speed multi-point full-duplex serial data switch.
High-speed multi-point full duplex serial data switches are well known in various forms, the switch being operable to change the interconnections between the outstations. One of the problems with such switches is the need to provide synchronisation between a central data switch and the outstations to and from which data is to be transmitted and received. Conventional asynchronous switches have to make provision for the regeneration of clock pulses at each receiver and for the synchronisation of these with the incoming data flow each time that the data flow stops and is restarted. This occurs each time that the switch configuration is changed. Such a requirement for synchronisation makes it necessary to provide a lock and capture time period during which no useful data may be passed, thus reducing the overall efficiency of the system. Whilst an alternative is to distribute clock pulses from a central clock to all outstations there are inherent difficulties in maintaining synchronisation due to noise, jitter, inherent delays, device tolerances, power supply and temperature variations and other problems. The paper given by De Ulio et al at the International Switching Symposium in Paris from the May 7-11 1979, entitled xe2x80x9cPerformance Objectives for the national network synchronizationxe2x80x9d, and reported at pages 559 to 566, relates to a system having a central reference oscillator, which is subject to just these problems. Japanese Patent publication JP-A-06327072 and Patent Abstracts of Japan, vol. 095, no. 002, Mar. 31, 1995 discloses a system in which closed-loop synchronisation is provided by detecting phase errors at a host station and transmitting an error signal to a synchronising clock at a substation, the synchronising clock providing timing signals to both the transmitter and the receiver of the substation.
It is an object of the invention to provide a closed-loop synchronisation arrangement for a data transmission system in which a central data switch and any of a plurality of data transceivers are maintained in constant synchronisation.
According to the present invention there is provided a closed-loop synchronisation arrangement for a data transmission system which includes a data switch including a clock generator and a plurality of ports each connecting the data switch to a separate transceiver, each port comprising a data transmitter, a data receiver, phase discrimination means connected between the switch data receiver and the switch data transmitter and operable to detect phase differences between the signals received by the data port receiver and those generated by the switch clock generator to generate a synchronising code for transmission to the transceiver, the transceiver comprising a data transmitter and a data receiver and synchronising means responsive to the synchronising code received by the receiver of the transceiver to adjust the phase of the data transmitted by the transmitter of the transceiver so as to maintain substantial synchronism with the associated switch data port, and a reference oscillator operable to provide a frequency reference signal to each part of the data transmission system.
In this specification the term xe2x80x9ctransceiverxe2x80x9d is used to denote an outstation comprising a data transmitter and receiver which may be connected to one or more other such transmitters and receivers by way of the central data switch.